You are given a byte$-$addressable toy computer that has a physical address space of $\backslash (2^\{10\}\backslash )$ bytes and a virtual address space is $\backslash (2^\{10\}\backslash )$ bytes. The computer has an $8-$entry fully associative TLB with the following entries:

The page table for process $465$ is shown below.

a$.$ How many bytes are in each page?

b$.$ How many bits of each virtual address is the virtual page number?

c$.$ How many bits of each physical address is the physical page number?

d$.$ How many bits of a virtual address are used to determine which TLB entries are accessed?

e$.$ How many entries of the TLB are compared for a TLB match?

f$.$ Consider the following memory accesses and fill out the table:

You are asked to add a $128-$byte write$-$through cache with $2-$byte cache blocks to enhance the performance of this computer. The cache access and address translation are to be performance simultaneously. In other word, the cache is indexed with virtual address, but performs tag comparison using physical addresses.

g$.$ To avoid synonym, we must ensure the cache index bits are only from the page offset. What is the minimum associativity of the cache?

h$.$ How many bits of a virtual address are used to index the cache? Which bits exactly?

i$.$ How many bits of a virtual address are used to determine which bytes in a block is accessed?

j$.$ How many bits are in a tag? What is the total tag storage in bits?