You are given three process corners for transistors, they are Slow$-$Slow, Fast$-$Fast and Typical$-$Typical. You are also given three corners for interconnect, they are Slow, Fast and Typical. You are asked to perform static timing analysis to check timing conditions. In the following figure, please describe how you will pick the standard cell for each part for checking setup and hold time respectively. Please also consider the clock tree, although it is not shown in the figure. You can first index the net name in the figure and refer to it when you answer the questions. Example Answer: Path $1$Setup: $$Net $1$: Slow Corner $$Logic: Slow$-$Slow Corner $....7.\backslash ((15\backslash \%)\backslash )$ You are given three process corners for transistors, they are Slow$-$Slow, Fast$-$Fast and Typical$-$Typical. You are also given three corners for interconnect, they are Slow, Fast and Typical. You are asked to perform static timing analysis to check timing conditions. In the following figure, please describe how you will pick the standard cell for each part for checking setup and hold time respectively. Please also consider the clock tree, although it is not shown in the figure. You can first index the net name in the figure and refer to it when you answer the questions.

Example Answer:

Path $1$ Setup:

$-$ Net $1$: Slow Corner

$-$ Logic: Slow$-$Slow Corner

$-....$