Question: Write Verilog module for a 4 - to - 2 Priority encoder with a Valid output as shown in the Truth Table below Inputs Outputs

Write Verilog module for a 4-to-2 Priority encoder with a Valid output as shown in the Truth Table below
Inputs Outputs D_(0) D_(1) D_(2) D_(3) x y 0000 V 100000 X 10001 X X 1010 X X X 111
Write Verilog module for a 4 - to - 2 Priority

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