You are the design manager to implement a shared$-$memory multicore system. Each

processor in the system has a private L$1$ instruction cache and private L$1$ data cache. The system uses a

snoopy protocol to ensure cache coherence between processors. To enhance the interconnection

bandwidth, a designer from your team suggests using a NoC $($network$-$on$-$chip$)$ with a torus topology

to connect all the processors. An NoC adopts a packet$-$switch scheme, and uses routers to forward the

data from the source node to the destination node. Multiple data transactions can be supported

concurrently. For this multicore system, please answer the following questions.