You are working at Hal Inc. designing the next generation CPU, implemented using CMOS transistor technology. A study of compiler C1 output shows the following instruction mix for a standard benchmark B on a CPU with 3 types of instructions:

Type            CPI      Mix

Arithmetic     3         65%

Memory         5        20%

Control           4       15%

Hal wants to sell a chip that can achieve a performance of 800 MIPS (on B). What clock frequency do you tell your VLSI team to design the chip for?

After extensive simulation, the VLSI team determines that the CPU of the previous part would produce120W of power. Unfortunately, your system can only dissipate 90W safely. What is the maximum MIPS rating that you can design for?

A certain program S requires 2 s. of CPU time, but must also do I/O of n bytes. I/O is of course slower, and an I/O operation of b bytes requires 2b+8 ms. (the 8 corresponds to a fixed startup time). The I/O system is designed so that I/O may be split into any number of transfers (e.g., n transfers of 1 byte each, n/2 transfers of 2 bytes each, ..., 1 n-byte transfer). The architecture team would prefer to do multiple small transfers to avoid hogging the I/O bus. However, the systems team constrains you so that S must take total time at most twice as long as its CPU portion. How best do you split the I/O transfers while keeping the architecture team happy (your answer will obviously be a function of the unknown/s). You may assume that n ranges over values for which your results make sense and do not need to use floor and ceiling functions (so your answer is an approximation).