Question: You have split caches (a 32KB instruction cache and a 32KB data cache) with the following specifications: Hit time is 1 clock cycle and miss

You have split caches (a 32KB instruction cache and a 32KB data cache) with the following specifications: Hit time is 1 clock cycle and miss penalty is 100 cycles There are 38.4 misses per 1000 instructions for 32KB data cache, and 1.36 misses per 1000 instructions for 32KB instruction cache. Assume 40% of instructions are data transfer instructions, CPI is 1 when all memory accesses hit in the cache.

(a) What is the overall average memory access time for the split caches?

(b) What is the overall average memory stalls per instruction for the split caches?

Step by Step Solution

There are 3 Steps involved in it

1 Expert Approved Answer

Step: 1 Unlock blur-text-image

Question Has Been Solved by an Expert!

Get step-by-step solutions from verified subject matter experts

Step: 2 Unlock

Step: 3 Unlock

Students Have Also Explored These Related Databases Questions!

Q2. Which has the lower miss rate: a 32KB instruction cache with a 32KB data cache or a 64KB unified cache? Use the miss rates from the following table, assuming 36% of the instructions are data...

Compute the overall (Cache) performance CPU: A processor runs at 3.0 GHz and has a CPI=1.5 for a perfect cache (i.e. without including the stall cycles due to cache misses). Assume that load and...

State all equations or formulas used and show all work done in the calculations. Submit only your work and answers. Question 1 A non-pipelined CPU with a clock frequency of 2 GHz has instruction...

In this exercise, we will look at the different ways cache capacity affects overall performance. In general, proportional to capacity. Assume that main memory accesses take 20 ns and that cache...

In this exercise, we will look at the different ways cache capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns...

Program in C a cache simulator, the cache simulator will take in a config file like this on command line: sampleconfig.cfg: 8 1 16 1 100 1 The .cfg sets 8 byte blocks, Direct mapped cache (0 would be...

ADVANCED COMPUTER ARCHITECTURE CPCS504 Assignment1 Spring 2021 /1442 Due Date 1st March 2021 Chapter1: 1. In Example 1 of Section 1.2.1, we assumed that the cache miss penalty was 20 cycles. With...

4. (33 pts.) A superscalar computer has Level 1 split Data and Instruction Caches, Level 2 (Combined) Cache, Main Memory, and a Hard Disk. The ideal CPI would be 1 if all the memory accesses resulted...

ABC Ltd has issued a 5 year zero coupon rate bond with maturity value of Sh.100,000. The bond is issued at a discount of 32%.Determine the rate of return of the bond. (4 marks)

BathGate Group has just completed its analysis of a project. The CFO has presented the following information to the board of directors: The initial cost of the project is $15,000. Sales are expected...

feedback and comment about the text below: Assessing risk is an important part of any organization when it comes to cyber security. Risk is typically assessed using the NIST management cycle ( NIST ,...

Compared with half a century ago, adoption has become _ _ _ _ _ _ _ _ _ common, but it is more open and acceptabl e , so we probably discuss it _ _ _ _ _ _ _ . fill in the blanks more or much less or...

What were the issues and solutions proposed by each team?

Were all members comfortable brainstorming in front of each other?

5. What information would the team members need?