Your Memory Components will have the following interfaces

$//$ The address bus is large enough that each module can contain a local address decode. This will save on multiple enables.

$//$ for now have each module dedicated to an address line. A more generic solution would be to decode the upper bits and have a specific range. Use all $4$ address bits $[15$:$12]$ in decode.

$//$ bits $15$:$12$ are used to memory map each peripheral

$//0=$ main memory

$//1=$ Instruction memory

$//2=$ Matrix ALU

$//3=$ Integer ALU

$//4=$ Internal Register

$//5=$ execution engine$$

$//$ bit $11-0$ are for addressing inside each unit.

$//$ nWrite $=0$ means databus is being written into on the falling edge of write

$//$ nRead $=0$ means it is expected to drive the databus while this signal is low and the address is correct until the nRead goes high independent of address bus.

$$

module InstructionMemory$($Clk$,$ Dataout, address, nRead, nReset$)$;

input logic nRead, nReset, Clk;

input logic $[15$:$0]$ address;

output logic $[255$:$0]$ Dataout;

$//////////////////////////////////////////$

$//////////$ instruction memory parameters. To be loaded into instruction memory at nreset $=0$;

parameter Instruct$1=32\text{'}$h $01\_02\_00\_01$;

$//$Add the number at memory location $8$ to location $9$ store in a temporary register $($ register $1)$

parameter Instruct$2=32\text{'}$h $10\_80\_08\_09$;

$//$Subtract the first matrix from the result in step $1$ and store the result somewhere else in memory.$$

parameter Instruct$3=32\text{'}$h $02\_03\_03\_00$;

$//$Transpose the result from step $1$ store in memory

parameter Instruct$4=32\text{'}$h $03\_04\_01\_$ff;

$//$Scale the result in step $3$ by the result from step $2$ store in a matrix register

parameter Instruct$5=32\text{'}$h $04\_05\_03\_80$;

$//$Multiply the result from step $4$ by the result in step $3,$ store in memory.$$

parameter Instruct$6=32\text{'}$h $00\_06\_04\_03$;

$//$Multiply memory location $0$ to location $1.$ Store it in memory location $0$A

parameter Instruct$7=32\text{'}$h $12\_0$A$\_00\_01$;

$//$Subtract Memory $01$ from memory location $0$A and store it in a register

parameter Instruct$8=32\text{'}$h $11\_0$A$\_01\_81$;

$//$Divide Memory location $0$A by the register in step $8$ and store it in location B

parameter Instruct$9=32\text{'}$h $13\_0$B$\_0$A$\_81$;

$//$STOP

parameter Instruct$10=32\text{'}$h ff$\_$ff$\_$ff$\_$ff;

$//////////////////////////////////////////////////////////////////$

module MainMemory$($Clk$,$ DataOut,DataIn, address, nRead, nWrite, nReset$)$;

input logic nRead, nWrite, nReset, Clk;

input logic $[15$:$0]$ address;

input logic $[255$:$0]$ Datain;

output logic $[255$:$0]$ Dataout;

$$

$//////////////////////////$

$//$ memory module top module

$//$

$//$

module top $()$;

logic $[255$:$0]$ InstructDataOut;

logic $[255$:$0]$ MemDataOut;

logic $[255$:$0]$ TestDataOut;

logic nRead,nWrite,nReset,Clk;

logic $[15$:$0]$ address;

InstructionMemory $$U$1($Clk$,$InstructDataOut, address, nRead,nReset$)$;

MainMemory $$U$2($Clk$,$MemDataOut,TestDataOut, address, nRead,nWrite, nReset$)$;

TestMem $$UTest$($Clk$,$nRead,nWrite,nReset,address,TestDataOut, InstructDataOut, MemDataOut$)$;

$$

$$ initial begin $//.$ setup to allow waveforms for edaplayground

$$$dumpfile$("$dump$.$vcd$")$;

$$$dumpvars$(1)$;

$$end

endmodule

$///////////////////////////////$