Question: Zintel is a Semiconductor chip assembly and test factory in Woodlands where wafers are singulated , assembled and tested. The semiconductor chips are processed through

Zintel is a Semiconductor chip assembly and test factory in Woodlands where
wafers are singulated, assembled and tested. The semiconductor chips are
processed through the machines in 'lots', Each lot contains a fixed number of
pieces or semiconductor chips known as lot size. The Zintel factory runs 24 hours
a day, 7 days a week throughout the year.
Assume that you are leading a project team to analyze the throughput (parts
produced per unit time), mean cycle time and Work in Process (WIP) at the Zintel
factory and to propose ways to improve the performance.
Assume that over the past few months, throughput at Zintel has averaged at 1440
lots per day, Average WIP in the line has been 9000 lots. The line capacity can be
simplified as shown in Table 1.
Table ?|?? Zintel Factory Manufacturing Data
(a) Compute the Raw process time, T0 and Constraint (bottleneck) rate, n for the
Semiconductor manufacturing line of Zintel factory.
(1 mark)
(b) Compute the Critical WIP (W0) for the Semiconductor manufacturing line at the
Zintel factory.
(1 mark)
(c) State Littles law and write down a mathematical expression for Practical Worst
Case (PWC) throughput performanoe.
(2 marks)
(d) Compute the approximate actual average cycle time of the Semiconductor
manufacturing line at the Zintel factory over the past few months based on the given
data.
(1 mark)
(e) Compute the coordinates of Best Case of Throughput against WIP, using the given
data including that of Table I and your answer from previous sections?
(1 mark)
(f) What are the coordinates of the actual Throughput-WIP performance point of the
manufacturing lines in the characteristics diagram?
(1 mark)
Note: Question 3 continues on page 5
(g) Compute Practical Worst Case (PWC) throughput, at a WIP level equal to that of
actual average WIP in the Zintel factory. Assume Raw process time T6, and
Constraint (bottleneck) rate rb are as computed before. State the coordinates of
computed operation point.
(2 marks)
(h) Compute the PWC WIP level required to achieve their current level of throughput
based on the performance of Zintel. Assume Raw process time T6 and Constraint
(bottleneck) rate n are as computed before. State the coordinates of computed
operation point.
(3 marks)
(i) Mark the actual Throughput-WIP performance point of the Zintel manufacturing
lines in the characteristics diagram of Throughput against WIP and draw the best
operating line in the characteristics diagram. Draw an approximate PWC curve
in the above drawn characteristics diagram of throughput against WIP, using the
two sets of coordinates of the PWC curve. (Clearly show all four coordinates in
the sketch)
(3 marks)
(j) State how well the Zintel Manufacturing line is performing in terms of
throughput, cycle time, and WIP using quantitative measures computed in
sections (a) to (i) above.
(2 marks)
 Zintel is a Semiconductor chip assembly and test factory in Woodlands

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