(a) Determine the noise margins of a CMOS inverter biased at \(V_{D D}=3.3 \mathrm{~V}\) with \((W / L)_{n}=2\) and \((W / L)_{p}=5\). Assume \(V_{T N}=0.4 \mathrm{~V}\) and \(V_{T P}=\) \(-0.4 \mathrm{~V}\).

(b) Repeat part (a) for \((W / L)_{n}=4\) and \((W / L)_{p}=12\).