(a) Given inputs \(A, B, C, \bar{A}, \bar{B}\), and \(\bar{C}\), design a CMOS circuit to implement the logic function \(Y=A \bar{B} \bar{C}+\bar{A} \bar{B} C+\bar{A} B \bar{C}\). The design should not include a CMOS inverter at the output.

(b) For \(k_{n}^{\prime}=2 k_{p}^{\prime}\), size the transistors in the design to provide equal switching times equal to the basic CMOS inverter with \((W / L)_{n}=1\) and \((W / L)_{p}=2\).