(a) Given inputs \(A, B, C, D\), and \(E\), design a CMOS circuit to implement the logic function \(\bar{Y}=A(B+C)+D+E\).

(b) Repeat part (b) of Problem 16.57 for this circuit.

Data From Problem 16.57:-

(a) Given inputs \(A, B, C, \bar{A}, \bar{B}\), and \(\bar{C}\), design a CMOS circuit to implement the logic function \(Y=A \bar{B} \bar{C}+\bar{A} \bar{B} C+\bar{A} B \bar{C}\). The design should not include a CMOS inverter at the output.

(b) For \(k_{n}^{\prime}=2 k_{p}^{\prime}\), size the transistors in the design to provide equal switching times equal to the basic CMOS inverter with \((W / L)_{n}=1\) and \((W / L)_{p}=2\).