Consider the basic TTL logic gate in Figure P17.32 with a fanout of 5. Assume transistor parameters of \(\beta_{F}=50\) and \(\beta_{R}=0.5\) (for each input emitter). Calculate the base and collector currents in each transistor for:

(a) \(v_{X}=v_{Y}=v_{Z}=0.1 \mathrm{~V}\), and

(b) \(v_{X}=v_{Y}=v_{Z}=5 \mathrm{~V}\).

+5 V 3.9 2.0 2.4 Q2 By o Tzo 23 0.8 Figure P17.32