Consider the class-AB MOSFET output stage shown in Figure P8.46. The circuit parameters are \(I_{\text {Bias }}=0.2 \mathrm{~mA}\) and \(R_{L}=1 \mathrm{k} \Omega\). The transistor parameters are \(k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=40 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T N}=0.8 \mathrm{~V}\), and \(V_{T P}=-0.8 \mathrm{~V}\). For the quiescent condition, assume \(v_{G S 3}=v_{S G 4}\) and \(v_{G S 1}=v_{S G 2}\). When \(v_{I}=-1.5 \mathrm{~V}, v_{O}=0\) and \(i_{D 1}=i_{D 2}=0.5 \mathrm{~mA}\). Determine the width-tolength ratio of each transistor.

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V+= 10 V Bias M3 M MA M2 ww Figure P8.46 V=-10 V RL -OVO