You are given this program:

A cache miss costs 6 clock cycles and a cache hit costs 2 clock cycles.

Assume that x and c do not interfere in the cache and that z and i are held in registers. If the cache line can hold W words, plot Ta, the total number of cycles required for the array accesses (x and c) during all 16 loop iterations for the values 2 ≤ W ≤ 8.

for (1-0, z-0; i