The test-and-set spin lock is the simplest synchronization mechanism possible on most commercial shared-memory machines. This spin lock relies on the exchange primitive to atomically load the old value and store a new value. The lock routine performs the exchange operation repeatedly until it finds the lock unlocked (i.e., the returned value is 0).

Unlocking a spin lock simply requires a store of the value 0.

As discussed in Section 4.7, the more optimized test-and-test-and-set lock uses a load to check the lock, allowing it to spin with a shared variable in the cache.

Assume that processors P0, P1, and P15 are all trying to acquire a lock at address 0x100 (i.e., register R1 holds the value 0x100). Assume the cache contents from Figure 4.37 and the timing parameters from Implementation 1 in Figure 4.38. For simplicity, assume the critical sections are 1000 cycles long.
a. Using the test-and-set spin lock, determine approximately how many memory stall cycles each processor incurs before acquiring the lock.
b. Using the test-and-test-and-set spin lock, determine approximately how many memory stall cycles each processor incurs before acquiring the lock.
c. Using the test-and-set spin lock, approximately how many bus transactions occur?
d. Using the test-and-test-and-set spin lock, approximately how many bus transactions occur?

DADDUI EXCH BNEZ R2 ,R0 , #1 R2,0(R1) R2, lockit tas : lockit: unlock: SW RO,0 (R1) R2, 0 (RI) R2, tatas R2 ,R0 , #1 R2,0 (R1) R2, tatas tatas LD BNEZ DADDUI EXCH BNEZ