Thermal stress testing is a common procedure used to assess the reliability of an electronic package. Typically, thermal stresses are induced in soldered or wired connections to reveal mechanisms that could cause failure and must therefore be corrected before the product is released. As an example of the procedure, consider an array of silicon chips (P_ch = 2300 kg/m³, C_ch = 710J/kg ∙ K) joined to an alumina substrate (P_sb = 4000 kg/m³ ∙ c_sb = 770 J/kg ∙ K) by solder balls (P_sd = 11,000 kg/m³, C_sd = 130 J/kg ∙ K). Each chip of width L_ch and thickness t_ch is joined to a unit substrate section of width L_sb and thickness t_ch by solder balls of diameter D.

A thermal stress test begins by subjecting the multichip module, which is initially at room temperature, to a hot fluid stream and subsequently cooling the module by exposing it to a cold fluid stream. The process is repeated for a prescribed number of cycles to assess the integrity of the soldered connections.

(a) As a first approximation, assume that there is negligible heat transfer between the components (chip/solder/substrate) of the module and that the thermal response of each component may be determined from a lumped capacitance analysis involving the same convection coefficient h. Assuming no reduction in surface area due to contact between a solder ball and the chip or substrate, obtain expressions for the thermal time constant of each component. Heat transfer is to all surfaces of a chip, but to only the top surface of the substrate. Evaluate the three time constants for L_ch = 15 mm, t_ch = 2 mm. L_sb = 25 mm, t_sb = 10 mm, D = 2 mm, and a value of h = 50 W/m² ∙ K, which is characteristic of an air stream. Compute and plot the temperature histories of the three components for the heating portion of a cycle, with T_i = 20°C and T_∞ = 80°C. At what time does each component experience 99% of its maximum possible temperature rise, that is, (T – T_i) / (T_∞ - T_i) = 0.99? If the maximum stress on a solder ball corresponds to the maximum difference between its temperature and that of the chip or substrate, when will this maximum occur?

(b) To reduce the time required to complete a stress test, a dielectric liquid could be used in lieu of air to provide a larger convection coefficient of h = 200 W/m² ∙ K. What is the corresponding savings in time for each component to achieve 99% of its maximum possible temperature rise?

Chip- (Peno Cchd "ch Lch Fluid Te, h Solder ball D. Psd. Csa) Substrate (Psbo Csb) Lsb