A microprocessor has a memory write timing as shown in Figure 3.19. Its manufacturer specifies that the width of the Write signal can be determined by T - 50, where T is the clock period in ns.
a. What width should we expect for the Write signal if bus clocking rate is 5 MHz?
b. The data sheet for the microprocessor specifies that the data remain valid for 20 ns after the falling edge of the Write signal. What is the total duration of valid data presentation to memory?
c. How many wait states should we insert if memory requires valid data presentation for at least 190 ns?
Figure 3.19
Timing of Synchronous Bus Operations

Clock Status lines Status signals Address lines Stable address Address enable Data lines Valid data in Read cycle Read Data Write l lines Valid data out cycle Write