The Intel 8088 microprocessor has a read bus timing similar to that of Figure 3.19, but requires four processor clock cycles. The valid data is on the bus for an amount of time that extends into the fourth processor clock cycle. Assume a processor clock rate of 8 MHz.
a. What is the maximum data transfer rate?
b. Repeat but assume the need to insert one wait state per byte transferred.
Figure 3.19
Timing of Synchronous Bus Operations

Transcribed Image Text:

Clock Status lines Status signals Address lines Stable address Address enable Data lines Valid data in Read cycle Read Data Write l lines Valid data out cycle Write