Assume the following performance characteristics on a cache read miss: one clock cycle to send an address to main memory and four clock cycles to access a 32-bit word from main memory and transfer it to the processor and cache.
a. If the cache line size is one word, what is the miss penalty (i.e., additional time required for a read in the event of a read miss)?
b. What is the miss penalty if the cache line size is four words and a multiple, nonburst transfer is executed?
c. What is the miss penalty if the cache line size is four words and a transfer is executed, with one clock cycle per word transfer?