For the multiprocessor illustrated in Figure 4.42 implementing the protocol described in Figure 4.43 and Figure 4.44, assume the following latencies:
€¢ CPU read and write hits generate no stall cycles.
€¢ Completing a miss (i.e., do Read and do Write) takes Lack cycles only if it is performed in response to the Last Ack event (otherwise it gets done while the data is copied to cache).
€¢ A CPU read or write that generates a replacement event issues the corresponding
Get Shared or Get Modified message before the Put Modified message (e.g., using a write back buffer).
€¢ A cache controller event that sends a request or acknowledgment message (e.g., Get Shared) has latency Lsend_msg cycles.
€¢ A cache controller event that reads the cache and sends a data message has latency Lsend_data cycles.
€¢ A cache controller event that receives a data message and updates the cache has latency Lrcv_data.
€¢ A memory controller incurs Lsend_msg latency when it forwards a request message.
€¢ A memory controller incurs an additional Linv cycles for each invalidate that it must send.
€¢ A cache controller incurs latency Lsend_msg for each invalidate that it receives (latency is until it sends the Ack message).
€¢ A memory controller has latency Lread_memory cycles to read memory and send a data message.
€¢ A memory controller has latency Lwrite_memory to write a data message to memory (latency is until it sends the Ack message).
€¢ A non data message (e.g., request, invalidate, Ack) has network latency Lreq_msg cycles
€¢ A data message has network latency Ldata_msg cycles.
Consider an implementation with the performance characteristics summarized in Figure 4.45.

Figure 4.45 Directory coherence latencies
For the sequences of operations below, the cache contents of Figure 4.42, and the directory protocol above, what is the latency observed by each processor node?
a. P0: read 100
b. P0: read 128
c. P0: write 128 d. P0: write 120 e. P0: write 108

Implementation 1 Action Latency send msg send data rev data read memory write memory inv ack req ms data msg 20 15 100 20 4 15 30