The performance of a single-level cache system for a read operation can be characterized by the following equation:
Ta = Tc + (1 - H)Tm
where Ta is the average access time, Tc is the cache access time, Tm is the memory access time (memory to processor register), and H is the hit ratio. For simplicity, we assume that the word in question is loaded into the cache in parallel with the load to processor register. This is the same form as Equation (4.2).
a. Define Tb = time to transfer a line between cache and main memory, and W = fraction of write references. Revise the preceding equation to account for writes as well as reads, using a write-through policy.
b. Define Wb as the probability that a line in the cache has been altered. Provide an equation for Ta for the write-back policy.