Question: Consider the advanced directory protocol described above and the cache contents from Figure 4.42. What are the sequence of transient states that the affected cache

Consider the advanced directory protocol described above and the cache contents from Figure 4.42. What are the sequence of transient states that the affected cache blocks move through in each of the following cases? In all cases, assume that the processors issue their requests in the same cycle, but the directory orders the requests in top-down order. Assume that the controllers' actions appear to be atomic (e.g., the directory controller will perform all the actions required for the DS --> DM transition before handling another request for the same block).
a. P0: read 120 P1: read 120
b. P0: read 120 P1: write 120 <-- 80
c. P0: write 120 P1: read 120
d. P0: write 120 <-- 80 P1: write 120 <-- 90
e. P0: replace 110 P1: read 110
f. P1: write 110 <-- 80 P0: replace 110
g. P1: read 110 P0: replace 110

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