Consider the micro-channel cooling arrangement of Problem 8.101. However, instead of assuming the entire chip and cap to be at a uniform temperature, adopt a more conservative (and realistic) approach that prescribes a temperature of Ts = 350 K at the base of the channels (x = 0) and allows for a decrease in temperature with increasing x along the side walls of each channels.

(a) For the operating conditions prescribed in Problem 8.101 and a chip thermal conductivity of kch = 140 W/m ∙ K, determine the water outlet temperature and the chip power dissipation. Heat transfer from the sides of the chip to the surroundings and from the side walls of a channel to the cap may be neglected. Note that the spacing between channels, δ = S – W, is twice the spacing between the side wall of an outer channel and the outer surface of the chip. The channel pitch is S = L/N, where L = 10 mm is the chip width and N = 50 is the number of channels.

(b) The channel geometry prescribed in Problem 8.101 and considered in part (a) is not optimized and larger heat rates may be dissipated by adjusting related dimensions. Consider the effect of reducing the pitch to a value of S = 100μm while retaining a width of W = 50μm and a flow rate per channel of m1 = 10–4kg/s.

#1 Chip, keh -Microchannel 8-- 8/2- Cap (Adiabatic)