Implement the half-adder of Fig. 15.3 using only (a) NAND gates; (b) NOR gates. x ty (x+yxy)

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Implement the half-adder of Fig. 15.3 using only
(a) NAND gates;
(b) NOR gates.
Implement the half-adder of Fig. 15.3 using only
(a) NAND gates;
(b)
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