Derive and sketch the complete small-signal equivalent circuit for the device of Problem 1.15 with V GS = 1 V, V DS = 2 V, and V SB = 1 V. Use ψ 0 = 0.7 V, C sb0 = C db0 = 20 fF, and C gb = 5 fF. Overlap capacitance from gate to source and gate to

Chapter 1, Problems #16

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Derive and sketch the complete small-signal equivalent circuit for the device of Problem 1.15 with VGS = 1 V, VDS = 2 V, and VSB = 1 V. Use ψ0 = 0.7 V, Csb0 = Cdb0 = 20 fF, and Cgb = 5 fF. Overlap capacitance from gate to source and gate to drain is 2fF.

Data from Prob. 1.15:

An NMOS transistor has parameters W = 10 µm, L=1 µm, k’ =194 µA/V2, λ = 0.024 V−1, tox = 80 Aͦ, ϕf = 0.3 V, Vt0 = 0.6 V, and NA = 5×1015 atoms/cm3. Ignore velocity saturation effects.

Related Book For answer-question

Analysis and Design of Analog Integrated Circuits

5th edition

Authors: Paul R. Gray, ‎ Paul J. Hurst Stephen H. Lewis, ‎ Robert G. Meyer

ISBN: 978-0470245996