Design a simple MOS current mirror of the type show in Fig. 4.4 to meet the following constraints:

Figure 4.4: Hypothetical band-gap reference circuit

(a) Transistor M₂ must operate in the active region for values of V_OUT to within 0.2 V of ground.

(b) The output current must be 50 µA.

(c) The output current must change less than 1 percent for a change in output voltage of 1 V.

Make M₁ and M₂ identical. You are to minimize the total device area within the given constraints. Here the device area will be taken to be the total gate area (W × L product). Assume X_d = 0 and take other device data from Table 2.4.

Table 2.4

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VREjon) Vce -2 mVC VBElon) Sum VOUT = VRE(on) + MV, Vr MVT м VT generator +3300 ppm/°C = + 0.085 mV°C Value Value n-Channel p-Channel Parameter Symbol Transistor Transistor Units Substrate doping NA, ND 5 x 105 4 x 1016 Atoms/cm Gate oxide thickness lox 80 80 Metal-silicon work function Фия -0.6 -0.1 cm/V-s Channel mobility Minimum drawn channel 450 150 Larwa 0.4 0.4 pm length Source, drain junction depth Source, drain side diffusion Overlap capacitance per unit gate X) La Cd 0.15 0.18 um 0.09 0.09 um 0.35 0.35 fF/um width Threshold adjust implant (box dist) impurity type effective depth х, 0.16 0.16 effective surface Nsi 4 x 106 3 x 1016 Atoms/cm concentration -0.8 100 Nominal threshold voltage V, Napoly 0.6 Polysilicon gate doping 100 Atoms/cm concentration Poly gate sheet resistance Source, drain-bulk junction R, 0.2 0.4 fF/um? capacitances (zero bias) Source, drain-bulk junction capacitance grading 0.5 0.4 coefficient Source, drain periphery capacitance (zero bias) Source, drain periphery capacitance grading coefficient Source, drain junction built-in potential Срио 1.2 2.4 F/μη 0.4 0.3 0.7 0.7 Os Surface-state density 101 Atoms/cm? dX4 dVps Channel-length modulation 0.02 0.04 дm/v parameter