Using the schematics from Fig. 5.35 and Problem 5.24, design the output stage shown in Fig. 5.32 to satisfy the following requirements.

(a) V_DD = V_SS = 2.5 V.

(b) The standby power dissipation should be no more than 70 mW.

(c) R_L = 100 Ω.

(d) The maximum allowed gain error with zero offsets and all transistors operating in the active region is 1 percent.

(e) In Fig. 5.35,(W/L)₁₇ = (W/L)₁/100 and (W/L)₁₃ = (W/L)₁₄ = (W/L)₁/10. Similarly, in Problem 5.24, (W/L)₂₇ = (W/L)₂/100 and (W/L)₂₃ =(W/L)₂₄ = (W/L)₂/10.

(f) To control the quiescent current, the maximum allowed error-amplifier gain is 5.

(g) Your solution is allowed to use four ideal current sources, two in each error amplifier. To allow these ideal current sources to be replaced by real transistors in a design step not required in this problem, the voltage across each ideal current source in Fig. 5.35 must be at least 0.5 V when V_o ‰¥ 0. Similarly, the voltage across each ideal current source in the complementary circuit from Problem 5.24 must be at least 0.5 V when V_o ‰¤ 0.

(h) To guarantee that M₁₆ and M₂₆ do not cut off under these conditions, assume I_TAIL = 5 I_BIAS in Fig. 5.35 and I_TAILP = 5 I_BIASP in Problem 5.24.

(i) For both n- and p-channel transistors, assume that λ = 0, L_d = X_d = 0, and ignore the body effect. Use L_drwn = 1 µm for all transistors, and use Table 2.3 for other transistor parameters.

(j) The distortion of the output stage should be minimized under the above conditions.

Verify your design using SPICE.

Figure 5.35:

Figure 5.32:

VDD M14 M13 M1 M17 M12 M11 V. M16 M15 O TAIL IBIAS -Vss