For this problem, you will create a series of small snippets that illustrate the issues that arise when using functional units with different latencies. For each one, draw a timing diagram similar to Figure C.38 that illustrates each concept, and clearly indicate the problem.

a. Demonstrate, using code different from that used in Figure C.38, the structural hazard of having the hardware for only one MEM and WB stage.

b. Demonstrate a WAW hazard requiring a stall.

Figure C.38

Clock cycle number 5 Instruction 2 3 4 10 6 7 11 MUL.D FO,F4,F6 M1 M4 WB M7 IF ID M2 M5 M6 MEM MEM IF ID EX WB ID EX IF MEM WB A1 A2 ADD.D F2,F4, F6 IF ID A4 MEM WB WB IF ID EX MEM EX IF ID MEM WB ... L.D F2,0(R2) IF ID EX MEM WB