Exercise 2.28 The following table contains MIPS assembly code for a lock.

try: MOV R3,R4 MOV R6,R7 LL R2,0(R2)

LL R5,0(R1)

SC R3,0(R1)

SC R6,0(R1)

BEQZ R3,try MOV R4,R2 MOV R7,R5 2.28.1 [5] <2.11> For each test and fail of the store conditional, how many instructions need to be executed?

2.28.2 [5] <2.11> For the load locked/store conditional code above, explain why this code may fail.

2.28.3 [15] <2.11> Rewrite the code above so that the code may operate correct.

Be sure to avoid any race conditions.

Each entry in the following table has code and also shows the contents of various registers. The notation, “($s1)” shows the contents of a memory location pointed to by register $s1. The assembly code in each table is executed in the cycle shown on parallel processors with a shared memory space.

a.

Processor 1 Processor 2 Cycle Processor 1 MEM Processor 2

$t1 $t0 ($s1) $t1 $t0 0 1 2 99 30 40 ll $t1, 0($s1) ll $t1, 0($s1) 1 sc $t0, 0($s1) 2 sc $t0, 0($s1) 3 2.21 Exercises 207 b.
Processor 1 Processor 2 Cycle Processor 1 MEM Processor 2 $s4 $t1 $t0 ($s1) $s4 $t1 $t0 0 2 3 4 99 10 20 30 try: add $t0, $0, $s4 1 try: add $t0, $0, $s4 ll $t1, 0($s1) 2 ll $t1, 0($s1) 3 sc $t0, 0($s1) 4 beqz $t0, try sc $t0, 0($s1) 5 add $s4, $0, $t1 beqz $t0, try 6 2.28.4 [5] <2.11> Fill out the table with the value of the registers for each given cycle.