Exercise 4.1 Different instructions utilize different hardware blocks in the basic single-cycle implementation. The next three problems in this exercise refer to the following instruction:

Instruction Interpretation

a. add Rd,Rs,Rt Reg[Rd]=Reg[Rs]+Reg[Rt]

b. lw Rt,Offs(Rs) Reg[Rt]=Mem[Reg[Rs]+Offs]

4.1.1 [5] <4.1> What are the values of control signals generated by the control in Figure 4.2 for this instruction?

4.1.2 [5] <4.1> Which resources (blocks) perform a useful function for this instruction?

4.1.3 [10] <4.1> Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?

Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks.
Latencies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruction. For the remaining three problems in this exercise, assume the following resource latencies:
I-Mem Add Mux ALU Regs D-Mem Control

a. 400ps 100ps 30ps 120ps 200ps 350ps 100ps

b. 500ps 150ps 100ps 180ps 220ps 1000ps 65ps 4.1.4 [5] <4.1> What is the critical path for a MIPS AND instruction?
4.1.5 [5] <4.1> What is the critical path for a MIPS load (LD) instruction?
4.1.6 [10] <4.1> What is the critical path for a MIPS BEQ instruction?