Exercise 4.12 In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:

IF ID EX MEM WB

a. 300ps 400ps 350ps 500ps 100ps

b. 200ps 150ps 120ps 190ps 140ps 4.12.1 [5] <4.5> What is the clock cycle time in a pipelined and nonpipelined processor?
4.12.2 [10] <4.5> What is the total latency of a lw instruction in a pipelined and nonpipelined processor?
4.12.3 [10] <4.5> If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?
The remaining problems in this exercise assume that instructions executed by the processor are broken down as follows:
ALU beq lw sw

a. 50% 25% 15% 10%

b. 30% 25% 30% 15%
4.12.4 [10] <4.5> Assuming there are no stalls or hazards, what is the utilization (% of cycles used) of the data memory?
4.12.5 [10] <4.5> Assuming there are no stalls or hazards, what is the utilization of the write-register port of the “Registers” unit?
4.12.6 [30] <4.5> Instead of a single-cycle organization, we can use a multicycle organization where each instruction takes multiple cycles but one instruction fi nishes before another is fetched. In this organization, an instruction only goes through stages it actually needs (e.g., ST only takes four cycles because it does not need the WB stage). Compare clock cycle times and execution times with singlecycle, multi-cycle, and pipelined organization.