Exercise 4.13 In this exercise, we examine how data dependences affect execution in the basic fi ve-stage pipeline described in Section 4.5. Problems in this exercise refer to the following sequence of instructions:

Instruction sequence

a. lw $1,40($6)

add $6,$2,$2 sw $6,50($1)

b. lw $5,–16($5)

sw $5,–16($5)

add $5,$5,$5 4.13.1 [10] <4.5> Indicate dependences and their type.
4.13.2 [10] <4.5> Assume there is no forwarding in this pipelined processor.
Indicate hazards and add nop instructions to eliminate them.
4.13.3 [10] <4.5> Assume there is full forwarding. Indicate hazards and add nop instructions to eliminate them. The remaining problems in this exercise assume the following clock cycle times:
Without forwarding With full forwarding With ALU-ALU forwarding only

a. 300ps 400ps 360ps

b. 200ps 250ps 220ps 4.13.4 [10] <4.5> What is the total execution time of this instruction sequence without forwarding and with full forwarding? What is the speed-up achieved by adding full forwarding to a pipeline that had no forwarding?
4.13.5 [10] <4.5> Add nop instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage)?
4.13.6 [10] <4.5> What is the total execution time of this instruction sequence with only ALU-ALU forwarding? What is the speed-up over a no-forwarding pipeline?