Exercise 4.16 The fi rst three problems in this exercise refer to the following MIPS instruction:

Instruction

a. lw $1,40($6)

b. add $5,$5,$5 4.16.1 [5] <4.6> As this instruction executes, what is kept in each register located between two pipeline stages?

4.16.2 [5] <4.6> Which registers need to be read, and which registers are actually read?

4.16.3 [5] <4.6> What does this instruction do in EX and MEM stages?

The remaining three problems in this exercise refer to the following loop. Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, and that the pipeline has full forwarding support. Also assume that many iterations of this loop are executed before the loop exits.

Loop

a. Loop: lw $1,40($6)

add $5,$5,$8 add $6,$6,$8 sw $1,20($5)

beq $1,$0,Loop

b. Loop: add $1,$2,$3 sw $0,0($1)

sw $0,4($1)

add $2,$2,$4 beq $2,$0,Loop 4.16.4 [10] <4.6> Show a pipeline execution diagram for the third iteration of this loop, from the cycle in which we fetch the fi rst instruction of that iteration up to (but not including) the cycle in which we can fetch the fi rst instruction of the next iteration. Show all instructions that are in the pipeline during these cycles (not just those from the third iteration).

4.16.5 [10] <4.6> How often (as a percentage of all cycles) do we have a cycle in which all fi ve pipeline stages are doing useful work?

4.16.6 [10] <4.6> At the start of the cycle in which we fetch the fi rst instruction of the third iteration of this loop, what is stored in the IF/ID register?