Exercise 4.17 Problems in this exercise assume that instructions executed by a pipelined processor are broken down as follows:

add beq lw sw

a. 50% 25% 15% 10%

b. 30% 15% 35% 20%

4.17.1 [5] <4.6> Assuming there are no stalls and that 60% of all conditional branches are taken, in what percentage of clock cycles does the branch adder in the EX stage generate a value that is actually used?

4.17.2 [5] <4.6> Assuming there are no stalls, how often (percentage of all cycles)

do we actually need to use all three register ports (two reads and a write) in the same cycle?

4.17.3 [5] <4.6> Assuming there are no stalls, how often (percentage of all cycles)

do we use the data memory?

Each pipeline stage in Figure 4.33 has some latency. Additionally, pipelining introduces registers between stages (Figure 4.35), and each of these adds an additional latency. The remaining problems in this exercise assume the following latencies for logic within each pipeline stage and for each register between two stages:

IF ID EX MEM WB Pipeline register

a. 100ps 120ps 90ps 130ps 60ps 10ps

b. 180ps 100ps 170ps 220ps 60ps 10ps 4.17.4 [5] <4.6> Assuming there are no stalls, what is the speed-up achieved by pipelining a single-cycle datapath?

4.17.5 [10] <4.6> We can convert all load/store instructions into register-based

(no offset) and put the memory access in parallel with the ALU. What is the clock cycle time if this is done in the single-cycle and in the pipelined datapath? Assume that the latency of the new EX/MEM stage is equal to the longer of their latencies.

4.17.6 [10] <4.6> The change in Exercise 4.17.5 requires many existing lw/sw instructions to be converted into two-instruction sequences. If this is needed for 50%

of these instructions, what is the overall speed-up achieved by changing from the fi vestage pipeline to the four-stage pipeline where EX and MEM are done in parallel?