Exercise 4.26 This exercise explores how exception handling affects control unit design and processor clock cycle time. The fi rst three problems in this exercise refer to the following MIPS instruction that triggers an exception:

Instruction Exception

a. add $0,$1,$2 Arithmetic overfl ow

b. lw $2,40($3) Invalid data memory address 4.26.1 [10] <4.9> For each stage of the pipeline, determine the values of exception-related control signals from Figure 4.66 as this instruction passes through that pipeline stage.

4.26.2 [5] <4.9> Some of the control signals generated in the ID stage are stored into the ID/EX pipeline register, and some go directly into the EX stage. Explain why, using this instruction as an example.

4.26.3 [10] <4.9> We can make the EX stage faster if we check for exceptions in the stage after the one in which the exceptional condition occurs. Using this instruction as an example, describe the main disadvantage of this approach.

The remaining three problems in this exercise assume that pipeline stags have the following latencies:

IF ID EX MEM WB

a. 300ps 320ps 350ps 350ps 100ps

b. 200ps 170ps 210ps 210ps 150ps 4.26.4 [10] <4.9> If an overfl ow exception occurs once for every 100,000 instructions executed, what is the overall speed-up if we move overfl ow checking into the MEM stage? Assume that this change reduces EX latency by 30ns and that the IPC achieved by the pipelined processor is 1 when there are no exceptions.

4.26.5 [20] <4.9> Can we generate exception control signals in EX instead of in ID?

Explain how this will work or why it will not work, using the “bne $4,$5,Label”

instruction and these pipeline stage latencies as an example.

4.26.6 [10] <4.9> Assuming that each Mux has a latency of 40ps, determine how much the control unit has to generate the fl ush signals? Which signal is the most critical?