Exercise 4.27 This exercise examines how exception handling interacts with branch and load/store instructions. Problems in this exercise refer to the following branch instruction and the corresponding delay slot instruction:

Branch and delay slot

a. beq $1,$0,Label sw $6,50($1)

b. beq $5,$0,Label nor $5,$4,$3 4.27.1 [20] <4.9> Assume that this branch is correctly predicted as taken, but then the instruction at “Label” is an undefi ned instruction. Describe what is done in each pipeline stage for each cycle, starting with the cycle in which the branch is decoded up to the cycle in which the fi rst instruction of the exception handler is fetched.

4.27.2 [10] <4.9> Repeat Exercise 4.27.1, but this time assume that the instruction in the delay slot also causes a hardware error exception when it is in MEM stage.

4.27.3 [10] <4.9> What is the value in the EPC if the branch is taken but the delay slot causes an exception? What happens after the execution of the exception handler is completed?

The remaining three problems in this exercise also refer to the following store instruction:

Store instruction

a. sw $6,50($1)

b. sw $5,60($3)

4.27.4 [10] <4.9> What happens if the branch is taken, the instruction at “Label”

is an invalid instruction, the fi rst instruction of the exception handler is the sw instruction given above, and this store accesses an invalid data address?

4.27.5 [10] <4.9> If load/store address computation can overfl ow, can we delay overfl ow exception detection into the MEM stage? Use the given store instruction to explain what happens.

4.27.6 [10] <4.9> For debugging, it is useful to be able to detect when a particular value is written to a particular memory address. We want to add two new registers, WADDR and WVAL. The processor should trigger an exception when the value equal to WVAL is about to be written to address WADDR. How would you change the pipeline to implement this? How would this sw instruction be handled by your modifi ed datapath?