Assuming stall-on-branch and no delay slots, what speedup is achieved on this code if branch outcomes are determined in the ID stage, relative to the execution where branch outcomes are determined in the EX stage?

In this exercise, we examine how resource hazards, control hazards, and ISA design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code:

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a. b. Label: Instruction sequence SW R16,12(R6) LW R16,8(R6) BEQ R5, R4, Label; Assume R5 != R4 ADD R5, R1, R4 SLT R5, R15, R4 SW R2,0 (R3) OR R1, R2, R3 BEQ R2, RO, Label; Assume R2 OR R2, R2, RO ADD R1, R4, R3. = RO