Question: Assuming there are no stalls, how often (percentage of all cycles) do we actually need to use all three register ports (two reads and a

Assuming there are no stalls, how often (percentage of all cycles) do we actually need to use all three register ports (two reads and a write) in the same cycle?

Problems in this exercise assume that instructions executed by a pipelined processor are broken down as follows: a. b. ADD 40% 60% BEQ 30% 10% LW 25% 20% SW 5% 10%

a. b. ADD 40% 60% BEQ 30% 10% LW 25% 20% SW 5% 10%

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