For each stage of the pipeline, what are the values of the control signals asserted by this instruction in that pipeline stage?

The first three problems in this exercise refer to the execution of the following instruction in the pipelined datapath from Figure 4.51, and assume the following clock cycle time, ALU latency, and Mux latency:

Figure 4.51

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a. b. Instruction LW R1,32(R2) OR R1, R5, R6 Clock Cycle Time 50ps 200ps ALU Latency 30ps 170ps Mux Latency 15ps 25ps