In the rest of this exercise, we assume that the following basic digital logic elements are available, and that their latency and cost are as follows:

The time given for a D-element is its setup time. The data input of a lip-lop must have the correct value one setup-time before the clock edge (end of clock cycle) that stores that value into the lip-lop.

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a. b. NOT AND Latency Cost Latency Cost Latency Cost 10ps 2 12ps 4 50ps 1 90ps 2 12ps 100ps 4 OR 2 XOR Latency Cost 14ps 120ps 6 3 D-Element Latency Cost 30ps 10 160ps 2