In this exercise, we will explore the control unit for a cache controller for a processor with a write buffer. Use the finite state machine found in Figure 5.40 as a starting point for designing your own finite state machines. Assume that the cache controller is for the simple direct-mapped cache described on page 465 (Figure 5.40 in Section 5.9), but you will add a write buffer with a capacity of one block. Recall that the purpose of a write buffer is to serve as temporary storage so that the processor doesn€™t have to wait for two memory accesses on a dirty miss. Rather than writing back the dirty block before reading the new block, it buffers the dirty block and immediately begins reading the new block. The dirty block can then be written to main memory while the processor is working.

Figure 5.40

1. What should happen if the processor issues a request that hits in the cache while a block is being written back to main memory from the write buffer?

2. What should happen if the processor issues a request that misses in the cache while a block is being written back to main memory from the write buffer?

3. Design a finite state machine to enable the use of a write buffer.×

Transcribed Image Text:

Cache Hit Idle Compare Tag Mark Cache Ready If Valid && Hit, Set Valid, SetTag, if Write Set Dirty Valid CPU request Cache Cache Miss Miss and and Old Block is Dirty Old Block is Clean Memary Ready Write-Back Allocate Memory Ready Write Old Block to Memory Read new block from Memory Memory Memory not Ready not Ready