Cache coherence concerns the views of multiple processors on a given cache block. The following data shows two processors and their read/write operations on two different words of a cache block X (initially X[0] = X[1] = 0). Assume the size of integers is 32 bits.

P1 P2
X[0] ++; X[1] = 3; X[0] = 5; X[1] +=2;

1. List the possible values of the given cache block for a correct cache coherence protocol implementation. List at least one more possible value of the block if the protocol doesn’t ensure cache coherency.

2. For a snooping protocol, list a valid operation sequence on each processor/cache to finish the above read/write operations.

3. What are the best-case and worst-case numbers of cache misses needed to execute the listed read/write instructions?
Memory consistency concerns the views of multiple data items. The following data shows two processors and their read/write operations on different cache blocks (A and B initially 0).

P1 P2

A = 1; B = 2; A+=2; B++; C = B; D = A;

4. List the possible values of C and D for an implementation that ensures both consistency assumptions on page 470.

5. List at least one more possible pair of values for C and D if such assumptions are not maintained.

6. For various combinations of write policies and write allocation policies, which combinations make the protocol implementation simpler?