One way to move the branch resolution one stage earlier is to not need an ALU operation in conditional branches. The branch instructions would be “BEZ Rd,Label” and “BNEZ Rd,Label”, and it would branch if the register has and does not have a zero value, respectively. Change this code to use these branch instructions instead of BEQ. You can assume that register R8 is available for you to use as a temporary register, and that an SEQ (set if equal) R-type instruction can be used.

This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor:

a. b. Label1: LW R2,0 (R2) BEQ OR SW R2, RO, Label; Taken once, then not taken R2, R2, R3 R2,0 (R5) LW R2,0 (R1) Label1: BEQ R2, RO, Labe12; Not taken once, then taken LW R3,0 (R2) BEQ ADD Label2: SW R3, RO, Labell; Taken R1, R3, R1 R1,0 (R2)