What CPI would be achieved if the X86 version of this loop is executed on a processor that internally translates these instructions into MIPS-like micro-operations, then executes these micro-operations on a 1-issue 5-stage pipeline with static scheduling. Note that the instruction count used in CPI computation for this processor is the X86 instruction count.

Problems in this exercise refer to the following loop, which is given as x86 code and also as an MIPS translation of that code. You can assume that this loop executes many iterations before it exits. When determining performance, this means that you only need to determine what the performance would be in the "steady state," not for the first few and the last few iterations of the loop. Also, you can assume full forwarding support and perfect branch prediction without delay slots, so the only hazards you have to worry about are resource hazards and data hazards. Note that most x86 instructions in this problem have two operands each. The last (usually second) operand of the instruction indicates both the first source data value and the destination. If the operation needs a second source data value, it is indicated by the other operand of the instruction. For example, "sub (edx),eax" reads the memory location pointed by register edx, subtracts that value from register eax, and puts the result back in register eax.

a. Label: x86 Instructions mov mov add mov mov cmp jne b. Label: add mov add add mov test jl -4(esp), eax -4(esp), edx (edi,eax, 4), edx edx, -4(esp) -4 (esp),eax 0, (edi,eax,4) Label 4, edx (edx), eax 4(edx), eax 8(edx), eax eax, -4(edx) edx, edx Label MIPS-like Translation r2,-4 (sp) r3,-4(sp) r2,r2,2 r2,r2, r4 Label: 1w 1w sll add 1w add SW 1w s11 add 1w bne Label: addi 1w 1 w add Tw add SW slt bne r2,0 (r2) r3, r3, r2 r3,-4(sp) r2,-4 (sp) r2,r2,2 r2,r2,r4 r2,0 (r2) r2, zero, Label r4, r4,4 r3,0 (r4) r2,4(r4) r2, r2, r3 r3,8(r4) r2, r2, r3 r2,-4(r4) r1, r4, zero rl,zero, Label