Question: The remaining three problems in this exercise refer to the following function, given in both C and x86 assembly. For each x86 instruction, we also

The remaining three problems in this exercise refer to the following function, given in both C and x86 assembly. For each x86 instruction, we also show its length in the x86 variable-length instruction format and the interpretation (what the instruction does). Note that the x86 architecture has very few registers compared to MIPS, and as a result the x86 calling convention is to push all arguments onto the stack. The return value of an x86 function is passed back to the caller in the EAX register.a. C Code int f(int a, int b, int c, int d) { if(a>b) return c: return d; } f: push %ebp mov mov %esp,%ebpb. void f(int a[], int n) [ int i; for(i=0;i!-n;i++) a[i]=0; } : 1B, push %ebp to stack : 2B, move %esp to


If the processor can execute two instructions per cycle, it must at least be able to read two consecutive instructions in each cycle. Explain how it would be done in MIPS and how it would be done in x86.

a. C Code int f(int a, int b, int c, int d) { if(a>b) return c: return d; } f: push %ebp mov mov %esp,%ebp 12(%ebp),%eax cmp %eax,8(%ebp) mov 16 (%ebp),%edx jle S pop %ebp. mov ret S: mov pop mov ret %edx, %eax 20 (%ebp),%edx %ebp %edx,%eax x86 Code : 1B, push %ebp to stack ; 2B, move %esp to %ebp : 3B, load 2nd arg into %eax ; 3B, compare %eax w/ 1st arg ; 3B, load 3rd arg into %edx : 2B, jump if cmp result is

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Instruction pipelining allows for the execution of many instructions per cycle in both MIPS and x86 architectures The two designs particular methods a... View full answer

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