Using a table similar to that shown in Figure 3.10, calculate 74 divided by 21 using the hardware described in Figure 3.8. You should show the contents of each register on each step. Assume both inputs are unsigned 6-bit integers.

Figure 3.8

Figure 3.10

Transcribed Image Text:

Divisor Shift right 64 bits Quotient 64-bit ALU Shift left 32 bits Remainder Control Write test |64 bits Iteration Step Quotient Divisor Remainder Initial values 0000 0010 0000 0000 0111 1: Rem = Rem – Div 0000 0010 0000 0110 0111 2b: Rem < 0= +Div, sll Q, QO = 0 0000 0010 0000 0000 0111 3: Shift Div right 0000 0001 0000 0000 0111 1: Rem = Rem – Div 0000 0001 0000 0111 0111 %3D 2b: Rem < 0 = +Div, sll Q, QO = 0 0000 0001 0000 0000 0111 3: Shift Div right 0000 0000 1000 0000 0111 1: Rem = Rem – Div 0000 0000 1000 0111 1111 %3D 3 2b: Rem < 0 = +Div, sll Q, QO = 0 0000 0000 1000 0000 0111 %3D 3: Shift Div right 0000 0000 0100 0000 0111 1: Rem = Rem – Div 0000 0000 0100 Oo00 0011 4 2a: Rem 20 = sll Q, QO = 1 0001 0000 0100 0000 0011 3: Shift Div right | 1: Rem = Rem – Div 2a: Rem 20 = sll Q, QO = 1 3: Shift Div right 0001 0000 0010 0000 0011 0001 0000 0010 O000 0001 0011 0000 0010 0000 0001 0011 0000 0001 0000 0001 1.