Using the first branch instruction in the given code as an example, describe the forwarding support that must be added to support branch execution in the ID stage. Compare the complexity of this new forwarding unit to the complexity of the existing forwarding unit in Figure 4.62.

This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor:

and $12, $2, $5 of Flash Clock 3 memory Iw $4,50(57) Clock 4 namiction mary ------ boq $1, $3,7 thand detection Rag Bubble (nop) Hand dat u Reg sub $10, $4, $8 boq $1, $3,7 EXMEM EXEM 1 botorect> Da MENW ab $10.... Data MENWW 1 botor-> botorect> (KEE