Question: Give an example of a program that will cause a branch penalty in the three-segment pipeline of Sec. 9-5. Example: Three-Segment Instruction Pipeline A typical

Give an example of a program that will cause a branch penalty in the three-segment pipeline of Sec. 9-5.

Example: Three-Segment Instruction Pipeline A typical set of instructions for a RISC processor are listed in

Now consider the hardware operation for such a computer. The control section fetches the instruction from

Delayed Load Consider now the operation of the following four instructions: 1. LOAD: R1M[address 1]

Clock cycles: 1. Load RI 2. Load R2 3. Add R1 + R2 4. Store R3 (a) Pipeline timing with data conflict Clock

Example: Three-Segment Instruction Pipeline A typical set of instructions for a RISC processor are listed in Table 8-12. We see from this table that there are three types of instructions. The data manip- ulation instructions operate on data in processor registers. The data transfer instructions are load and store instructions that use an effective address ob- tained from the addition of the contents of two registers or a register and a displacement constant provided in the instruction. The program control in- structions use register values and a constant to evaluate the branch address, which is transferred to a register or the program counter PC.

Step by Step Solution

3.48 Rating (161 Votes )

There are 3 Steps involved in it

1 Expert Approved Answer
Step: 1 Unlock

In threesegment pipeline the segments are 1instruction fetch IF 2 instruction decode ID 3execute EX ... View full answer

blur-text-image
Question Has Been Solved by an Expert!

Get step-by-step solutions from verified subject matter experts

Step: 2 Unlock
Step: 3 Unlock

Students Have Also Explored These Related Computer System Architecture Questions!