Give an example that uses delayed branch with the three-segment pipeline of Sec. 9-5.

Example: Three-Segment Instruction Pipeline A typical set of instructions for a RISC processor are listed in Table 8-12. We see from this table that there are three types of instructions. The data manip- ulation instructions operate on data in processor registers. The data transfer instructions are load and store instructions that use an effective address ob- tained from the addition of the contents of two registers or a register and a displacement constant provided in the instruction. The program control in- structions use register values and a constant to evaluate the branch address, which is transferred to a register or the program counter PC.