Include a two-input AND gate with the register of Fig. 2-6 and connect the gate output to the clock inputs of all the flip-flops. One input of the AND gate receives the clock pulses from the clock pulse generator. The other input of the AND gate provides a parallel load control. Explain the operation of the modified register.

Fig. 2-6

Transcribed Image Text:

Clock Clear 10 "1 N 13 D D с C D U D U e a e a Ao A₁ A₂ A3